FPGA​/ASIC Design Engineer

Chipton‑Ross is seeking an FPGA/ASIC Design Engineer for a contract opportunity in Camden, NJ.

• At least 3 years of experience implementing complex algorithms targeting ASIC/FPGAs.
• Proficiency in VHDL and FPGA design/debug with Xilinx FPGA/Vivado.
• Excellent analytical/debug skills.
• Good verbal, written, and presentation skills.
• US citizenship required; VHDL experience required for all candidates.
• Mid‑senior level – >5 years of VHDL experience;
  Xilinx FPGA design experience with Vivado.
• Hands‑on experience with multiple complex designs (architecture, design, verification, synthesis, STA).
• Experience with Ethernet protocol beyond IP instantiation is a plus.
• Experience mentoring EDA CDC/Lint/AC/RDC.

• Architect, implement, verify, and validate complex FPGA and/or ASIC systems.
• Write and debug tests/sequences for end‑to‑end simulation on UVM framework, System Verilog assertions, and C++ SW‑driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.
• Develop architectures for high‑throughput designs involving cryptographic algorithms with high‑speed protocols such as NVMe, PCIe/SRIOV, 10G‑400G Ethernet, TCP/IP, and IP development/integration targeting ARM SoC FPGAs (e.g., Xilinx MPSOC) and/or ASICs.

• High‑Level Synthesis (HLS) with Vivado.
• Embedded software C++ (OOP) and System Verilog assertions (SVA).
• Knowledge of high‑speed protocols (PCIe, TCP/IP, Ethernet).

• Bachelor of Science in Electrical Engineering or Computer Science (or equivalent). Master of Science in Electrical Engineering or Computer Science preferred. Education must be accredited.

Full‑time, Monday–Friday 08:00 am–05:00 pm.

• Active secret clearance required.