Field-Programmable Gate Arrays Engineer

Clearance:
Active Secret Clearance Required

Position Summary:

We are seeking a mid-to-senior level FPGA/ASIC Design Engineer to join a high-impact engineering team developing advanced communication products for National Security applications.

This role will be responsible for the architecture, design, implementation, verification, validation, and software integration of complex FPGA and/or ASIC systems.

Key Responsibilities

• Develop architectures and implement high-throughput, complex FPGA/ASIC designs
• Design and implement cryptographic algorithms using VHDL
• Work with high-speed protocols including PCIe, NVMe, SR-IOV, 10G-400G Ethernet, and TCP/IP
• Develop and integrate IP targeting ARM SoC FPGAs, including Xilinx MPSoC, and/or ASICs
• Perform hands-on FPGA/ASIC architecture, design, verification, synthesis, and static timing analysis (STA)
• Develop and debug UVM-based test benches and simulation sequences
• Develop System Verilog Assertions (SVA) for verification
• Develop and debug C++ software-driven validation on SoC evaluation boards running Linux
• Support clock-domain crossing (CDC), lint, and reset-domain crossing (RDC) analysis
• Work with modern FPGA/ASIC EDA tools and verification methodologies

Required Qualifications

• 3+ years of experience implementing complex algorithms targeting FPGAs and/or ASICs
• 5+ years of hands-on VHDL experience
• Strong experience with Xilinx FPGA design and Vivado
• Proven experience taking complex designs through architecture, design, verification, synthesis, and STA
• Experience with FPGA/ASIC verification and validation
• Active Secret Clearance required
• Bachelor’s degree in Electrical Engineering, Computer Science, or related field
• Master’s degree in Electrical Engineering or Computer Science is a plus

Preferred / Plus Qualifications

• Hands-on experience with Ethernet protocols, beyond simply integrating Ethernet IP
• Experience with Mentor/Siemens EDA tools, including CDC, Lint, AC, and RDC
• Experience with High-Level Synthesis (HLS) using Vivado
• Embedded C++ / Object-Oriented Programming
• System Verilog Assertions (SVA)
• Knowledge of high-speed protocols such as PCIe, TCP/IP, and Ethernet
• Experience with Synopsys Design Compiler, Prime Time, Synplify, Questa, or similar EDA tools
• Experience with UVM, VIP, CDC, and HLS methodologies

Equal Opportunity Employer/Veterans/Disabled

Benefit offerings include medical, dental, vision, term life insurance, short-term disability insurance, additional voluntary benefits, commuter benefits and 401K plan. Our program provides employees the flexibility to choose the type of coverage that meets their individual needs. Available paid leave may include Paid Sick Leave, where required by law; any other paid leave required by Federal, State or local law; and Holiday pay upon meeting eligibility criteria.

Disclaimer:
These benefit offerings do not apply to client-recruited jobs and jobs which are direct hire to a client

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The Company will consider qualified applicants with arrest and conviction records.