ASIC Design Verification Technical Leader

The application window is expected to close on: 06/01/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Cisco’s Client Optics Group (COG) designs & delivers the high‑speed optical transceivers and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of innovative IM/DD optics and silicon photonic platforms that enable customers to deploy industry‑leading optical technologies within data centers with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground‑breaking optical solutions by designing, developing, and testing some of the most advanced pluggable and co‑packaged optics (CPO) being developed in the industry.

You will work with Cisco's best‑in‑class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G, 1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high‑performance networks that support emerging technologies including AI/ML workloads and next‑generation data center architectures.

• Define and lead verification methodology and standards across multiple projects, coordinating activities across multiple sites.

• Lead verification at block & chip level with various high‑speed IPs integrated like ODSP, D2D IP, Ser Des XSR/PAM4, Integrated drivers/TIA, and control functions.

• Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency.

• Mentor and coach verification engineers, driving continuous improvement in technical skills and execution.

• Debug complex silicon and system‑level issues during bring‑up phases.

• Support post‑silicon bring‑up and optimize integration and performance.

• Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC Design Verification experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design Verification experience.

• Experience in System Verilog, UVM, and verification methodologies.

• Experience owning and delivering verification for large‑scale SoCs or subsystems.

• Experience leading verification teams or projects.

• Experience in scripting and automation such as Python, Perl, TCL, or Shell Scripts.

• Strong experience with UVM (Universal Verification Methodology) for developing scalable, reusable, and coverage‑driven verification environments.

• Expertise in verification of Ser Des IP, D2D PHY IP, ODSP & integrated transceiver features, CPU sub‑system & Protocols (Ethernet, UCIE, UAL, SPI/I2C, etc.).

• Experience influencing design for testability and verification.

• Proven experience in troubleshooting and debugging.

• Experience with Formal Verification, hardware description languages (HDLs) such as Verilog/System Verilog.

• Experience with emulation and prototyping platforms (Veloce, HAPS).

• Experience collaborating with architecture and design teams on verification strategy.

The starting salary range posted for this position is $ to $ and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below.

For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability…