Principal ASIC Design Engineer

Responsibilities

Max Linear is seeking a Principal ASIC Design Engineer to join our Digital ASIC Design group. The Digital ASIC team delivers innovative and scalable ASIC solutions addressing complex challenges in the optical and wireless communications domain.

In this senior technical role, you will lead the micro‑architecture, and RTL design of Digital Signal Processing (DSP) modules such as filters, modulators/demodulators, and custom DSP blocks. You will also lead the integration of DSP subsystems into larger SoC platforms.

This position requires a strong understanding of digital communication systems, solid fundamentals in digital design and CMOS logic, and hands‑on experience with industry‑standard design and verification methodologies. Proficiency with modern ASIC design and verification tools is essential, and low‑power design experience ishighly desirable.

The ideal candidate is a curious, highly motivated engineer with a relentless drive to learn, innovate, and solve complex problems. You bring a “never give up” attitude and thrive when tackling technically demanding challenges. You value collaboration across disciplines and leverage the differences in skill sets with cross‑domain teams to contribute to collective problem‑solving. You aspire to make a lasting technical impact while continuously raising the bar for design quality and engineering excellence.

• BE/M.Tech in Electronics Engineering
• 15+ years of experience in Digital ASIC implementation at subsystem level or chip level including RTL design skills using Verilog, System Verilog or VHDL
• Strong analytical and problem‑solving skills
• Proved expertise in translating engineering requirements to working ASIC solutions meeting PPA
• Strong fundamentals and proven expertise in digital logic design, CMOS technology and ASIC design methodology
• Strong fundamentals in basic circuit design, device physics
• Strong fundamentals in programming, CPU architecture and SOC systems
• Specialization in Digital Signal Processing or Communication systems
• Passion for learning and engineering great solutions
• Block level verification using SV, UVM, Python or C using industry standard tools
• Basic knowledge and ability to synthesize and perform STA with industry standard tools either for ASIC or FPGA
• Proven written and verbal communication skills that demonstrate clarity of thought and conviction
• Working knowledge of one or more scripting languages and ability to use them to automate/accelerate design and analysis tasks