Silicon Photonics Packaging Technical Leader- (Hybrid
Listed on 2026-07-03
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Engineering
Electrical Engineering, Electronics Engineer, Systems Engineer, Packaging Engineer
Packaging Technical Leader
As a Packaging Technical Leader, you will be responsible for the development and qualification of advanced packaging solutions for Cisco's next generation optical transceiver products.
Serve as the primary technical interface for the Client Optics Group with top-tier Outsourced Semiconductor Assembly & Test (OSAT) driving advanced package assembly, test, and qualification for silicon photonics products.
Lead the design and layout of test vehicles to validate packaging processes; conduct rigorous design reviews for complex substrates, ensuring alignment with signal/power integrity requirements and manufacturing capabilities.
Cross-functional technical leadership to proactively identify and mitigate risks, resolve highly complex assembly issues, and establish best-in-class quality and reliability standards across the supply chain.
Work collaboratively with other internal teams to influence package architecture and provide expert guidance on DfM, DfR, contributing to the definition of critical process parameters for HVM. Engage deeply in substrate design, materials selection, and reviews.
Present technical findings and recommendations to cross-functional teams and stakeholders.
Stay informed on emerging packaging technologies and industry trends, contributing to the evaluation of new materials, processes, and architectures.
Minimum QualificationsMasters Degree in Mechanical Engineering, Electrical Engineering, Physics, Materials Science, or a related field with 8+ years of experience in Photonics or Semiconductor Packaging Industry or a PhD in Mechanical Engineering, Electrical Engineering, Physics, Materials Science, or a related field with 3+ years of experience in Photonics or Semiconductor Packaging Industry
Proven experience in advanced Silicon Photonic package technology development, such as 2.5D/3D integration, TSV, flip-chip, stacking, hybrid integration, wafer-level packaging, and package technology qualification methods
Prior experience of package design & architecture, including substrate design and chip fabrication.
Experience with advanced substrate manufacturing processes and materials and their impacts to device level signal and power integrity
Experience with industry-standard design and simulation software (e.g., Cadence, klayout, Ansys or similar tools).
Preferred QualificationsPrior experience to work within and lead projects with highly cross-functional and geographically distributed technical teams.
Experience with co-packaged optics is a plus
Experience with volume manufacturing
Experience with mechanical and thermal modeling and simulation software
Experience in advanced problem-solving methodologies (e.g., 8D, FMEA, statistical process control) and data analysis skills.
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