Senior ASIC Design Verification Engineer
Job in
Carlsbad, San Diego County, California, 92002, USA
Listed on 2026-07-10
Listing for:
MaxLinear, Inc.
Full Time
position Listed on 2026-07-10
Job specializations:
-
Engineering
-
Quality Assurance - QA/QC
Job Description & How to Apply Below
Responsibilities
We are looking for a Senior Staff ASIC Design Verification Engineer to lead complex verification execution and contribute significantly to IP, Subsystem, and SoC-level verification. This role requires strong hands‑on expertise, ownership of verification deliverables, and the ability to apply advanced methodologies and AI-assisted workflows to ensure quality and on‑time tape‑out. You will focus on:
- Lead and execute verification activities at the IP, Subsystem, and SoC levels
- Define verification test plans and contribute to overall verification strategy
- Develop, enhance, and maintain reusable UVM‑based verification components and environments
- Drive functional and code coverage closure and debug complex verification issues
- Own key verification deliverables from development through sign‑off
- Apply AI‑assisted techniques to improve debug speed, test generation, coverage analysis, and regression efficiency
- Analyze verification metrics and continuously improve verification quality and productivity
- Collaborate closely with design, architecture, validation, and cross‑functional teams
- Contribute to verification best practices, automation initiatives, and process improvements
- Bachelor’s or Master’s degree in Electronic Engineering or a related field
- 8–12 years of hands‑on ASIC Design Verification experience
- Strong experience in IP, Subsystem, and SoC verification, preferably in networking or packet‑processing domains
- Solid experience building and maintaining scalable UVM‑based verification environments
- Strong proficiency in:
- System Verilog, UVM, Verilog
- C/C++
- Good understanding of verification methodologies, including directed and constrained‑random testing, coverage‑driven verification, and gate‑level simulations
- Experience with Linux/Unix environments and scripting languages such as Python, Perl, or Shell
- Working knowledge of high‑speed protocols such as Ethernet, PCIe, USB 3.0, and SERDES
- Exposure to SystemC and DSP is a plus
- Experience leveraging AI‑assisted verification tools or workflows is highly desirable
- Strong problem‑solving skills, attention to detail, and effective communication abilities
Position Requirements
10+ Years
work experience
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