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Application Specific Integrated Circuit Verification Engineer

Job in Carlsbad, San Diego County, California, 92002, USA
Listing for: Avacend Inc
Full Time position
Listed on 2026-08-11
Job specializations:
  • Engineering
    Test Engineer, Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 180000 USD Yearly USD 120000.00 180000.00 YEAR
Job Description & How to Apply Below

Location:

100% onsite Allentown, PA or Carlsbad, CA

Duration: 8/24/2026 to 8/27/2027

Job Description:

Job overview

Join our innovative team developing next-generation silicon solutions for Client's silicon one group. We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. You will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. Our team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences.

Key Job Responsibilities

Develop and implement Universal Verification Methodology (UVM) based verification environments.

Create comprehensive verification plans at both block and system levels.

Design and implement verification components including assertions, traffic generators, agents, and scoreboards.

Collaborate with cross-functional teams to evaluate design testability and verification requirements.

Lead debug efforts and provide solutions for complex technical challenges.

Basic Qualifications

Bachelor's degree in Electrical Engineering or a related field.

UVM Based testbench development.

Experience in ASIC or SOC verification.

Demonstrated experience in developing test plans and verification infrastructure.

Practical knowledge of verification methodologies from block level to system level.

Proficiency in System Verilog.

Experience in identifying and resolving complex design and verification issues.

Timing and gate level simulation experience.

Preferred Qualifications

Bachelors/master's degree in electrical or communications engineering or a related field.

Experience with formal verification techniques including abstraction and end-to-end checking.

Experience with industry-standard tools and scripting languages (Python or Perl) for automation.

System Verilog coding and debug.

AI based CAD efficiency improvisation initiatives

High speed serial protocols preferred UCIe, PCIE etc

Analog debug experience including DAC/ADC & calibrations white-box verification.

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