Senior Design Engineer

Responsibilities

• Design DDR SDRAM memory controllers and high performance ASIC for embedded processors using the Final Level Cache Architecture.
• Understand the system requirements of the digital functions and develop specifications.
• Define micro-architecture and conduct logic design applying knowledge in Computer Architecture, including: out-of-order execution, super scalar and pipeline, data hazard, cache/memory subsystems, CDC, and DDR SDRAM controller.
• Conduct RTL logic design with Verilog and/or System Verilog using tools, including:
  Synopsys VCS, Verdi, Spyglass, and Design Compiler, Cadence Incisive NC-verilog, NC-sim, and Xcelium.
• Perform logic synthesis, IP level verification, timing analysis, and resolve timing violations using Synopsys Prime Time.
• Report logic design issues, optimize design, perform CDC and resolve errors in cache and memory subsystem.
• Support the Design Verification team by providing design insights for test planning, debugging, and fixing failing test cases.
• Support all design integration activities like LINT, CDC, and synthesis.

• Master’s degree in Electrical Engineering and two years of experience in research and development of embedded processors and DDR SDRAM controller
• Logic design, logic synthesis, and verification and timing analysis of high performance ASIC
• Develop methods to improve design, and resolve errors involving cache/memory subsystem and CDC
• Logic design of various components in memory controller using RTL (mainly Verilog / System Verilog)
• Perform logic synthesis using Synopsys Design Compiler
• Experience in the micro-architecture definition of memory controllers, design verification and debugging
• Perform timing analysis and identify fixes on any timing violations using Synopsys Prime Time.

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