Lead Design Engineer

Cadence is a pioneering company in electronic design automation, developing software, hardware, and IP to enable advanced semiconductor chip design. We partner with leading technology companies across consumer, automotive, aerospace, and health sectors.

• Implement, verify, and perform timing closure to tape out Palladium and Protium SOCs.
• Work on RTL synthesis and floor planning.
• Build clock trees and perform optimizations.
• Close timing, IR drop, and physical verification.
• Review and document designs for taping out.
• Interface with Front End RTL design teams and Back End Verification teams.

• BS degree in Electrical Engineering with a minimum of 5 years of experience, or MS with a minimum of 3 years of experience.
• Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus, and Pegasus.
• Experience with advanced technologies such as 5nm, 3nm, and 2nm nodes.
• Experience using Linux servers and script development using Shell, Perl, TCL, or Python.
• Detailed knowledge of industry‑standard interfaces such as PCI Express, DDR, LPDDR, SRAM, and UCIe.

Equal Employment Opportunity Policy:
Cadence is committed to equal employment opportunity throughout all levels of the organization. Cadence is a proud equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence participates in the E‑Verify program in certain U.S. locations as required by law.