Sr Electrical Engineer – Design Verification - FPGA​/ASIC; Onsite

Overview

Avionics FPGA/ASIC engineer position in Cedar Rapids, IA. On‑site U.S. citizen required. Strong background in design verification for ASIC, FPGA, and SoPC with experience in safety‑critical digital hardware.

• Develop verification plans based on requirements capture, decomposition, and traceability.
• Architect and implement advanced constrained‑random and directed verification environments (UVM/System Verilog).
• Create, develop, and maintain reusable verification components, test benches, sequences, and functional coverage models.
• Perform ASIC/FPGA/SoPC verification using simulation, inspection, analysis, and hardware test methods.
• Conduct functional, code, and assertion coverage analysis and drive closure against verification goals.
• Apply best‑practice verification techniques including linting, CDC analysis, LEC, assertions, and regression automation.
• Collaborate with design teams to review architecture, interface specifications, and RTL implementation for testability and completeness.
• Generate DO‑254 DAL‑A verification artifacts and support certification activities for Airborne Electronic Hardware (AEH).
• Participate in technical peer reviews and FAA SOI audits.
• Contribute to engineering bids, support RFIs/RFPs, and provide accurate estimation for verification scope and effort.
• Communicate effectively across engineering, program management, and customer teams.
• Mentor junior verification engineers and recommend workflow/tool enhancements for continuous improvement.
• May perform responsibilities associated with project engineering as required.

• Degree in STEM (Bachelor or higher) and minimum 5 years of relevant experience, or an advanced degree in a related field.
• Experience developing test benches and verification environments in System Verilog, VHDL, and/or Verilog.
• Hands‑on experience with verification and simulation tools such as Questasim, Vivado, Libero, and Synplify Pro.
• Understanding of common digital interfaces (PCIe, DDR, Ethernet, I2C, ARINC
  429, CAN, etc.).
• Experience verifying timing behavior, device‑level timing constraints, and clock domain crossings.
• Experience with scripting languages such as Python, Perl, Linux shell, or C/C++.
• Ability to work independently and collaboratively with globally distributed, cross‑functional engineering teams.

• Strong experience with UVM and constrained‑random verification methodology.
• Knowledge of DO‑254 processes and verification‑related design assurance activities.
• Familiarity with chip‑level verification best practices including functional coverage, code coverage, assertions, and LEC.
• Experience with video or networking technologies.
• Demonstrated ability to manage cost, schedule, and performance for verification activities.
• Basic risk management experience including identification, quantification, and mitigation planning.

• Competitive salary range: $86,800 – $165,200.
• Medical, dental, and vision insurance.
• Three weeks of vacation for newly hired employees.
• Generous 401(k) plan with employer matching funds and separate employer retirement contribution.
• Tuition reimbursement program and student loan repayment program.
• Life insurance and disability coverage.
• Optional coverages (pet, home, auto, additional life, critical illness, legal,  protection).
• Birth, adoption, and parental leave benefits.
• Employee Assistance Plan with counseling sessions.
• Wellness incentives and rewards program.
• Access to virtual doctor visits and second‑opinion program.
• Child and elder care services.
• Relocation assistance may be available.

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status.