×
Register Here to Apply for Jobs or Post Jobs. X

Senior Principal FPGA​/ASIC Engineer - Lead RTL

Job in Cedar Rapids, Linn County, Iowa, 52404, USA
Listing for: Prattwhitney
Full Time position
Listed on 2026-07-21
Job specializations:
  • Engineering
    Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 132400 - 251600 USD Yearly USD 132400.00 251600.00 YEAR
Job Description & How to Apply Below
Position: Senior Principal FPGA/ASIC Engineer - Lead RTL & DO-254

RTX in Cedar Rapids, IA, seeks a senior engineer to lead ASIC/FPGA/SoPC digital design, RTL coding, and verification. You will develop constrained random UVM environments, perform synthesis and timing analyses, and support airworthiness certification artifacts.

The role requires strong Linux scripting and proficiency with VHDL/Verilog/System Verilog, plus collaboration across global teams on aggressive schedules.

#J-18808-Ljbffr
Position Requirements
10+ Years work experience
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
 
 
 
Search for further Jobs Here:
(Try combinations for better Results! Or enter less keywords for broader Results)
Location
Increase/decrease your Search Radius (miles)
0
200
Filters
Education Level
Experience Level (years)
Posted in last:
Salary