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Senior Technical Staff Engineer- Verification

Job in Chandler, Maricopa County, Arizona, 85249, USA
Listing for: FHLB Des Moines
Full Time position
Listed on 2026-02-14
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually.

We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our ; we affectionately refer to it as the
* Aggregate System
* and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over  without a great team dedicated to empowering innovation. People like you.

Visit our  page to see what exciting opportunities and company  await!
*
* Job Description:

** We are seeking a highly skilled and experienced Design Verification Engineer to join our team in developing cutting-edge machine learning acceleration solutions for edge computing. This role involves developing and verifying next-generation AI/ML acceleration hardware platforms. The ideal candidate will have a strong background in silicon hardware verification from system modeling to RTL to GDSII, with experience in microcontroller and neural processor unit subsystem verification in embedded systems.  

Join our team and be a part of the fast-growing, cutting-edge technology!
*
* Key Responsibilities:

*** Hands-on system-level and block-level verification of designs targeting FPGA platforms and production ICs
* Development of test plans, coverage plans, and verification project schedules.
* Define and lead development of System Verilog/UVM verification environments to achieve functional verification goals
* Understand the system level use cases and develop comprehensive SoC level verification plan based on product specification
* Track and report overall progress of the team driving simulation debug at RTL, power aware(UPF) and gate level simulations (GLS)
* Review all technical deliverables from team members and guide team members to meet quality and the schedule
* Support debug/analysis of Post Silicon issues with validation, applications, design, and test teams
** Requirements/

Qualifications:

*** Bachelors in ECE/EE/CS or related specializations with 15+ years of industry experience in IP/SoC verification
* Expertise in System Verilog, UVM, Embedded C, and scripting (Python or similar)
* Expertise in digital design fundamentals and ability to debug complex designs at RTL and Gate level
* Familiarity with power aware verification flows advanced low power techniques and tools such as UPF/CPF and power aware verification
* Experience providing technical leadership within a cross functional design/verification team
* Ability to collaborate on setting and achieving team goals
* Experience supporting transparent project management throughout the new product development lifecycle
* Excellent written and verbal communication skills with the ability to present and convey complex ideas
*
* Preferred Qualifications:

*** Masters in ECE/EE/CS or related specializations
* Good understanding of NPU/GPU acceleration, hardware acceleration techniques, and edge computing applications.
* Experience and knowledge of FPGA architectures and implementation of RTL designs in FPGA systems.
* Familiar with management systems such as Polarion and Atlassian (Jira, Confluence) tool suites.
* Knowledge of security and privacy considerations in edge computing and cyber security development/analysis methods using ISO-21434 workflow requirements.
* Understanding of Functional Safety Development and analysis methods using ISO-26262 workflow requirements.
** Travel Time:
** 0% - 25%
** Physical Attributes:
** Feeling, Hearing, Seeing, Talking, Works Alone, Works Around Others
*
* Physical Requirements:

** 80% sitting, 10% standing, 10% walking
** Pay Range:
** We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and…
Position Requirements
10+ Years work experience
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