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Senior Mixed-Signal Verification Engineer; UVM

Job in Chandler, Maricopa County, Arizona, 85249, USA
Listing for: Cirrus Logic
Full Time position
Listed on 2026-04-24
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer, Electrical Engineering, Test Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
Position: Senior Mixed-Signal Verification Engineer (UVM)
A prominent silicon technology company in Arizona seeks an experienced Design Verification Engineer to join its team. This role involves collaborating with digital and analog designers to ensure high-quality mixed-signal IC solutions. Candidates should have a Bachelor’s, Master’s, or PhD in Electrical Engineering or related fields, with relevant experience in ASIC verification and HDLs like Verilog and System Verilog. The position offers a rigorous working environment with opportunities to advance verification methodologies.
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Position Requirements
10+ Years work experience
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