Senior Physical Design Application Engineer

Overview

Senior Applications and Solutions Engineer to provide technical support to Intel Foundry Services customers on PDKs, digital reference flows, and design signoff methodologies with specialized focus on Cadence tool suites. This role drives quality improvements in design kits through ASIC design reference flow validation and supports customers through successful tape-outs.

• Customer Technical Support & Implementation:
  Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies. Support and deliver ASIC/digital tool/flow/methodology solutions using Cadence tool suites to address customer issues and ensure successful tape-outs. Drive customer success through expert guidance on advanced CMOS process implementation.
• Quality Assurance & Documentation:
  Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review. Create application notes, technical content, and deliver training presentations to customers and internal teams. Establish and maintain quality assurance processes for design flow validation.
• Design Flow Development & Optimization:
  Develop and optimize digital design implementation flows for advanced CMOS processes. Support hierarchical and multi-voltage domain design approaches, timing and physical convergence. Build and maintain QA regression frameworks for design validation.

• Self-driven and results-oriented with ability to manage multiple tasks effectively.
• Strong teamwork skills to drive solutions for customer design implementation challenges.
• Analytical problem-solving capabilities for complex design issues.
• Excellent communication skills with experience in collaboration and customer feedback.

The minimum qualifications are required to be considered for this position. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• US Citizenship required;
  Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field of study.
• 4+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of experience in ASIC physical design implementation and/or ASIC design signoff (SoC/ASIC).
• 3+ years of experience in one of the following scripting languages (Python, Perl, Tcl, shell scripting).

• Preferred Qualifications:
  
  Active US Government Security Clearance with a minimum of Secret level;
  Postgraduate degree in Electrical/Computer Engineering or related STEM field;
  Customer-facing experience in technical support;
  
  Experience with state-of-the-art process technology (7nm and below);
  Hands-on experience in Cadence EDA-based ASIC design implementation including full-chip integration, synthesis, APR, STA, layout verification, reliability verification;
  Proficiency with Cadence EDA tools and flows:
  Innovus, Tempus, Tempus
  
  ECO, Pegasus, Voltus;
  Experience with Synopsys tools (Fusion Compiler, Prime Time, Prime ECO, ICV) is a plus;
  Experience with hierarchical and multi-voltage domain design, top-down design, budgeting, and cross-tool correlation.

• Opportunity to work with cutting-edge digital design technologies for foundry services.
• Direct customer engagement and technical leadership in advanced semiconductor design.
• Access to Intel's most advanced foundry technologies and comprehensive EDA tool suites.
• Competitive compensation and professional development in digital design methodologies and foundry services.
• Direct impact on foundry customer success and advanced semiconductor innovation.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary

Location:

US, Arizona, Phoenix;
Additional Locations: US, California, Santa Clara; US, Oregon, Hillsboro

Business group:
The Central Engineering Group (CEG) — Intel’s data-driven organization delivering scalable engineering solutions across Product Enablement, Custom ASIC, and Foundry Enablement.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

• Annual salary range: $ - $ USD; range reflects minimum to maximum target compensation across US locations.
• Hybrid work model available; candidates split time between on-site and off-site.
• Intel benefits, stock bonuses, health, retirement, vacation, and professional development opportunities.

Note:

This job posting includes information that may be subject to change. Intel is committed to Responsible Business Alliance compliance and…