Senior Mixed-Signal Verification Engineer

A leading technology company in Arizona is looking for a Design Verification Engineer to join its silicon design verification team. The ideal candidate will have extensive experience in ASIC verification, specifically with mixed-signal designs. Responsibilities include developing verification plans, performing functional verifications, and implementing UVM-based test benches. A Bachelor's, Master's, or PhD in Electrical or Computer Engineering is required, along with significant industry experience and strong skills in Verilog and System Verilog.

This role offers opportunities for collaboration and process improvement.
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