Physical Verification Engineer

Overview

The Aerospace, Defense & Government (ADG) Senior Physical Verification Application Engineer provides specialized technical support to Intel Foundry Services customers on layout verification and parasitic extraction. This critical role ensures successful customer tape‑outs by resolving complex physical design challenges, driving quality improvements in design kits, and delivering comprehensive technical guidance on advanced verification methodologies.

• Physical Verification Support & Issue Resolution
  :
  Provide comprehensive technical support to Intel Foundry Services customers on layout verification and parasitic extraction challenges; collaborate with internal Intel teams and external stakeholders (foundry customers' design teams, IP providers, and EDA vendors) on physical and layout design rules and extraction issue resolution; resolve complex verification challenges across advanced CMOS processes and ensure successful customer design implementations.
• Technical Content Development & Training
  :
  Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams; drive quality improvements in design kits and documentation to remove barriers to successful customer design tape‑outs; develop best‑practice guidelines for physical verification flows and methodologies across advanced process technologies.
• Verification Methodology Leadership
  :
  Lead optimization of physical verification flows for advanced CMOS processes (22nm and below); provide technical direction on layout verification methodologies including DRC, LVS, ERC, and PERC implementations; drive methodology improvements to streamline customer design workflows and enhance verification productivity.
• Customer Engagement & Technical Excellence
  :
  Deliver customer‑facing technical support focused on physical verification challenges and solutions; support customers through complex verification issues and advanced process technology adoption; ensure maximum customer satisfaction through expert guidance and responsive technical support.

• Self‑driven and results‑oriented with the capability to effectively manage multiple complex tasks.
• Strong analytical problem‑solving skills for complex physical verification challenges.
• Effective communication skills with experience in collaboration, active listening, and providing constructive feedback.

• U.S. citizenship required.
• Ability to obtain a U.S. Government Security Clearance.
• Bachelor’s degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
• 3+ years of experience with advanced CMOS processes (22nm and below).
• 3+ years of combined experience in layout verification and parasitic extraction (EDA tools).
• 3+ years of experience in one or more of the following scripting languages:
  Python, Perl, Tcl, and/or shell scripting.

• Active U.S. Government Security Clearance with a minimum of Secret level.
• Post‑graduate degree in Electrical / Computer Engineering, Computer Science, or a STEM related field.
• Hands‑on experience in one or more of the following areas: LVS, DRC, ERC, PERC.
• Experience with parasitic extraction tools (e.g., StarRC, Quantus, or xACT).
• Experience with major layout editing EDA tools and flows such as ICV, Calibre, and Pegasus.
• Rule deck coding experience in ICV, Calibre, or Pegasus EDA tools.
• Experience providing technical direction to engineering teams, including but not limited to customer support and driving methodologies to streamline design work.
• Customer‑facing experience.

• Opportunity to work with cutting‑edge physical verification technologies for aerospace, defense, and government applications.
• Direct customer engagement and technical leadership in advanced semiconductor verification.
• Access to Intel’s most advanced foundry technologies and comprehensive verification tool suites.
• Competitive compensation and professional development in physical verification methodologies and foundry services.
• Direct impact on national security through advanced semiconductor verification solutions.

• Competitive pay, stock bonuses, and benefit programs that include health, retirement, and vacation.

Annual salary range for U.S. locations: $ – $ USD.

Hybrid work model – split time between on‑site at an Intel site and off‑site.

Primary location:
Phoenix, Arizona, U.S. Additional locations:
Santa Clara, California, and Hillsboro, Oregon.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.