Analog Mixed Signal Modeling Engineer; UL

Analog Mixed Signal Modeling Engineer (UL - 02)

We are seeking creative and hardworking engineers to join our outstanding Analog/Mixed‑Signal team. You will collaborate with systems and design teams to facilitate top‑down design methodology, architectural exploration, and mixed‑signal integration, and work with chip and DV leads to plan, set up, and execute DMS & AMS verification. This position will play a vital role in streamlining development methodology for our organization.

• Contribute to a team that generates & verifies advanced analog circuit equivalent models to support analog design, UVM verification, and HW/SW validation platforms
• Collaborate with system architects and designers to streamline architectural exploration of next‑generation IP
• Develop behavioral models using System Verilog Real Number Modeling (SV‑RNM), User‑defined Types (SV‑UDT), and Verilog AMS
• Develop DMS & AMS test plans, test benches, and verification methodologies to verify micro‑architectures
• Collaborate with multi‑functional teams to streamline chip‑level integration and maintain continuity of design, verification, and modeling feature drop plans
• Serve as primary mixed‑signal design regression debug support
• Develop DMS & AMS test platforms and execute DMS & AMS test plans
• Contribute to analog design reviews and recommend enhancements for improved circuit design and partitioning
• Collaborate with UVM verification engineers to ensure all verification components are used for AMS‑UVM flow
• Contribute to development of automation tools for design, verification, and modeling

• Master’s degree or higher in Electrical Engineering or Computer Engineering
• Experience in development of mixed‑signal products
• Strong background in analog integrated circuit design and proficiency in interpreting circuit schematics
• Strong background in digital signal processing and control systems
• Strong background in System Verilog for real‑number modeling, test bench development, and verification
• Organized and detailed with strong cross‑functional communication skills
• Possess outstanding analytical and problem‑solving skills
• Proficient in use of AMS simulators

• Experience teaming closely with digital/analog designers, applications engineers, and manufacturing test to support both pre‑silicon verification and post‑silicon validation efforts
• Knowledge of signal processing and System Verilog Assertions and PSL Assertions
• Experience with database management methodologies (Perforce, GIT, etc.)
• Working knowledge of UVM verification flows
• Working knowledge of Formal verification flows
• Simulink & Simscape experience
• Python scripting experience

Employment decisions are made on the basis of job‑related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law. Cirrus Logic strives to select the best qualified applicant for any opening.