Electronic Design Engineer

Responsibilities

Lead Verilog design of digital control logic for mobile phone LNAs, TX controllers, and switches. This includes design and timing closure (TCL layout setup script generation, setup/hold/width timing violation fixing) using Cadence Innovus, RTL‑to‑GDS flow, area optimization, and DRC/LVS error resolution. Perform digital synthesis with Cadence Genus or Synopsys Design Compiler, generate timing constraints in TCL, and conduct Verilog/System Verilog design and verification.

Create test benches and verification through simulation using Xcelium, Verilog, and Python automation. Execute constraint creation, synthesis, and physical design/timing closure of mobile phone digital circuits with Cadence Innovus. Develop Python automation scripts to support design activities. Work in a hybrid setting: three days in the office and two days working from a location within reasonable commuting distance.

Minimum of a Master’s degree in Electrical Engineering or related field.

• 6+ months of experience (or an internship/co‑op, or 6 graduate credit hours) involving
• design and timing closure with Cadence Innovus (TCL layout setup, setup/hold/width timing violation fixing);
• RTL‑to‑GDS flow, area optimization, DRC/LVS error resolution;
• digital synthesis with Cadence Genus or Synopsys Design Compiler and timing constraint generation in TCL;
• Verilog/System Verilog digital design and verification, understanding of test benches, clocking, and auto‑checking;
• verification of Verilog code using simulation tools;
• Python scripting and proficiency in other scripting languages.

Equal Opportunity Employer (EOE).