DFT Application Engineer

DFT Application Engineer

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

Position Overview:

We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role supports Aerospace, Defense, and Government (ADG) customers in achieving successful tape-outs while ensuring the highest quality standards through comprehensive DFT solutions and customer engagement.

Key Responsibilities:

• Provide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfaction
• Work closely with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors to resolve complex technical issues
• Deliver customer-facing technical support and guidance on DFT implementation strategies
• Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations
• Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoff
• Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs
• Develop application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
• Create best practice guidelines and methodology documentation for DFT implementation across various design complexities
• Support knowledge transfer and capability building for both internal teams and customer organizations

Essential Skills & Attributes:

• Customer-Focused:
  Strong customer-oriented attitude and mindset with commitment to customer success
• Self-Motivated:
  Self-driven and results-oriented with ability to manage multiple complex tasks effectively
• Collaborative:
  Excellent teamwork skills to drive innovative solutions for customer design implementation challenges
• Analytical:
  Strong analytical problem-solving capabilities for complex DFT challenges
• Communication:
  Effective communication skills with experience in collaboration, active listening, and providing constructive technical feedback

Qualifications:

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• US Citizenship required
• Ability to obtain US Government Security Clearance
• Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field
• 3+ years of experience with advanced CMOS processes (22nm and below)
• 3+ years of combined experience in the following: implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level
• 2+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)

Preferred Qualifications:

• Active US Government Security Clearance with a minimum of Secret Level.
• Post-graduate degree in Electrical/Computer Engineering or STEM-related field
• Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability)
• Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designs
• Exper…