Senior Digital Verification Engineer

Senior Digital Verification Engineer

Primary

Location:

Chandler, Arizona, USA

Role

Summary:

The Advanced Power Systems group within NXP's Power and Energy Business Line is seeking a Senior Digital Verification Engineer to develop next-generation Power Management ICs (PMICs) for automotive and industrial applications. This role will lead digital verification from architecture review through verification signoff, ensuring functionality, quality, reliability, and compliance.

• Lead digital verification activities and drive successful project execution from planning through signoff.
• Define verification plans, methodologies, environments, regressions, coverage goals, and signoff criteria.
• Review product requirements, architecture specifications, microarchitecture, interfaces, and implementation plans.
• Develop and maintain advanced verification environments using System Verilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions.
• Create directed and constrained-random test scenarios to validate functionality, performance, robustness, and corner-case behavior.
• Define, implement, and analyze functional, code, and assertion coverage; drive coverage closure and signoff.
• Apply System Verilog Assertions (SVA), formal verification methodologies, and regression analysis to identify and resolve issues.
• Verify PMIC digital control, telemetry, diagnostics, safety, power sequencing, fault management, communication interfaces, and embedded control functions.
• Deliver verification collateral including test plans, environments, assertions, regressions, coverage reports, metrics, milestones, and requirements traceability.
• Drive methodology improvements, automation, reuse, and productivity while mentoring junior engineers and collaborating across global teams.

• BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years of semiconductor industry experience.
• Strong understanding of digital design fundamentals, FSMs, CDC, reset architecture, low-power design, and SoC integration.
• Expertise in Verilog, System Verilog, UVM/OVM, and class-based verification methodologies.
• Strong knowledge of constrained-random, coverage-driven verification, regression automation, and verification signoff.
• Hands-on experience developing test benches, drivers, monitors, scoreboards, assertions, and reusable verification IP.
• Experience with System Verilog Assertions (SVA), formal verification techniques, and low-power verification methodologies such as UPF/CPF.
• Knowledge of industry-standard protocols including AMBA, I²C, SPI, UART, CAN, LIN, DDR, and PCIe.
• Proficiency in Python, Perl, and UNIX/Linux shell scripting for automation.
• Familiarity with FPGA, emulation, or prototyping platforms such as HAPS, Palladium, or Zebu is a plus.
• Understanding of PMIC architectures and power management concepts is highly desirable.
• Experience using AI/LLM-based technologies to improve engineering productivity is a plus.
• Strong analytical, debugging, problem-solving, communication, leadership, mentoring, and cross-functional collaboration skills.