Senior Analog Mixed Signal Verification Engineer

Analog Mixed-Signal Verification Engineer

Primary

Location:

Chandler, Arizona, USA

• Lead analog and mixed-signal verification for automotive and industrial PMIC products from specification through verification signoff.
• Define verification strategies, environments, regressions, and coverage objectives for complex mixed-signal IPs, subsystems, and SoCs.
• Collaborate with cross-functional teams to ensure product quality, reliability, functional correctness, safety, and robustness.

• Review product requirements, architecture specifications, design documentation, programming models, interfaces, and implementation plans for automotive and industrial PMIC applications.
• Define and execute AMS verification strategies aligned with system, performance, quality, reliability, safety, power, and functional requirements.
• Lead AMS verification activities, including verification plans, methodologies, environments, regressions, documentation, schedules, coverage objectives, and milestone tracking.
• Develop and validate mixed-signal simulation environments, behavioral models, checkers, assertions, scoreboards, and reusable verification components using Verilog-AMS, System Verilog, UVM, and RNM.
• Drive verification execution through test planning, constrained-random verification, mixed-signal simulation, coverage analysis, regression management, debug, and signoff.
• Bridge digital and mixed-signal verification flows for robust block, subsystem, and top-level verification.
• Verify digital control, monitoring, telemetry, diagnostics, configuration, protection, power sequencing, and fault-management functions within PMIC and power-conversion products.
• Track development metrics including milestones, code and functional coverage, defect resolution, requirements traceability, and compliance with verification requirements.
• Drive methodology improvements to increase simulation efficiency, reuse, quality, productivity, and cost effectiveness across projects.
• Collaborate with analog, digital, validation, subsystem, SoC, applications, system, customer, product definition, and architecture teams while mentoring junior engineers.

• M.S. in Electrical Engineering, Computer Engineering, or a related field required.
• Minimum 10 years of experience in analog and mixed-signal IC verification and development, including technical leadership responsibilities.
• Strong understanding of analog and mixed-signal circuit fundamentals, including PMICs, DC-DC converters, LDOs, ADCs, DACs, PLLs, voltage references, bandgaps, and sensor interfaces.
• Expertise in AMS verification using Verilog-AMS, System Verilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM).
• Experience developing behavioral models and reusable verification environments for complex mixed-signal designs.
• Strong knowledge of coverage-driven verification, constrained-random verification, regression automation, and verification signoff processes.
• Experience with formal verification, low-power verification, and requirements traceability methodologies is highly desirable.
• Proficiency with industry-standard EDA tools from Cadence, Synopsys, and Siemens EDA.
• Experience with scripting languages such as Python, Perl, Tcl, or Shell for automation and productivity enhancement.
• Strong analytical and problem-solving skills with the ability to develop innovative solutions for complex technical challenges.
• Excellent written and verbal communication skills.
• Proven ability to lead cross-functional teams and collaborate effectively in a fast-paced product development environment.