Staff Design Verification Engineer (AI​/ML

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible.

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As a Staff Design Verification Engineer, you will develop and execute verification strategies for complex analog and mixed-signal ICs, from test planning through coverage closure. You will apply AI/ML techniques to improve regression efficiency, debug throughput, and coverage analysis. Your work will contribute to product quality and delivery across multiple business units, ensuring ADI's next-generation mixed-signal and power management products meet rigorous quality standards.

Apply AI/ML methodologies for failure clustering, regression triage, anomaly detection, and coverage optimization

Develop and execute verification plans, defining coverage models and success metrics for mixed-signal IC blocks and subsystems

Build and maintain System Verilog/UVM test benches, monitors, scoreboards, and automated checkers for mixed-signal verification

Perform functional coverage analysis and drive coverage closure toward tape-out readiness

Support silicon correlation by comparing simulation expectations against lab measurements and refining tests based on results

Participate in verification reviews, contributing technical analysis on coverage completeness and methodology improvements

Collaborate with design, applications, and test teams to ensure verification reflects real use-cases and operating conditions

MSEE or MSCE with 7+ years of IC verification experience, or PhD with 5+ years (BSEE/BSCE with equivalent depth considered) Strong proficiency in System Verilog and UVM with experience building coverage-driven verification environments for mixed-signal products Demonstrated ability to deliver verification through tape-out sign-off and production release Solid Python scripting skills with experience applying AI/ML techniques to enhance verification productivity Knowledge of formal verification, assertion-based methodology, and clock domain crossing analysis Proficiency with Cadence verification tools:
Xcelium (simulation), Jasper Gold (formal verification) Excellent presentation, technical writing, and communication skills

Curiosity and initiative to explore AI/ML techniques and emerging tools that can transform verification workflows, with an enthusiasm for discovering more effective ways of working Experience with mixed-signal and AMS verification techniques including Verilog-AMS, real-number modeling, and behavioral abstraction Experience with gate-level simulation, SDF back-annotation, and post-layout verification Strong analytical and problem-solving abilities Ability to work effectively in a collaborative team environment

Application of AI/ML-driven workflows for regression analytics, failure classification, and debug acceleration Block-level and subsystem-level verification ownership from specification analysis through coverage closure Mixed-signal verification environment development including analog behavioral modeling and digital-analog interface checking Test plan authoring, coverage model implementation, and regression management

Share AI/ML-driven improvements to verification workflows and best practices with team members Work with design, applications, and test teams to translate product requirements into verification coverage that reflects real operating conditions Contribute to verification reviews and cross-team technical discussions

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of…