Analog and Mixed Signal Design Engineer

Role Overview

Broadcom’s Central Engineering Group is seeking an experienced Mixed-Signal Analog Design Engineer to join our world-class team. In this position, you will design advanced on-die Process, Voltage, and Temperature (PVT) monitoring IP. You will work across a wide range of cutting-edge technologies, including the industry's most advanced process nodes and applications.

Broadcom’s Central Engineering Group is seeking an experienced Mixed-Signal Analog Design Engineer to join our world-class team. In this position, you will design advanced on-die Process, Voltage, and Temperature (PVT) monitoring IP. You will work across a wide range of cutting-edge technologies, including the industry's most advanced process nodes and applications.

• Circuit Design & Verification:
  Design schematic architectures for analog and mixed-signal blocks, including bandgaps, ADCs, DACs, voltage regulators, comparators, and GPIOs.
• Layout & Post-Layout Validation:
  Supervise layout design and verify post-layout design using SPICE simulations to ensure silicon success.
• Digital Modeling:
  Build behavioural and gate-level models for IPs and validate functionality through Verilog simulations.
• IP Delivery & Documentation:
  Create standard EDA tool views (including timing models), and author comprehensive datasheets and technical integration documents.
• Silicon Bring-up & Validation:
  Establish post-silicon testing guidelines and oversee the validation process by analysing and reviewing test data.

• MS or PhD in Electrical Engineering
• 6+ years of mixed-signal and analog design experience.

• Deep knowledge of core analog concepts including gain, bandwidth, stability, device physics, circuit reliability, process variation, and the statistical analysis of Monte Carlo simulation results.
• Strong understanding of layout effects on circuit performance.
• Familiarity with Verilog modelling, digital circuits, and standard digital implementation flows.

• Proficiency with Cadence Virtuoso and simulation platforms like Spectre, HSPICE, or Prime Sim.
• Experience with Synopsys Prime Time and Verilog simulators such as Xcelium or VCS.

• Excellent communication and teamwork skills.
• Proven ability to independently navigate complex, new, or unfamiliar engineering challenges.

• Prior experience building and delivering mixed-signal IPs.
• General familiarity with laboratory testing methodologies and common bench equipment to effectively guide lab teams.
• Proficiency in scripting languages (Python, Perl, SKILL) to automate design and verification tasks.
• Familiarity with ESD (Electrostatic Discharge) and latch‑up design rules.
• Silicon Failure Analysis (FA) and debugging skills.

The annual base salary range for this position is USD  To USD

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package:
Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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