Senior Digital Verification Engineer

Senior Digital Verification Engineer

Required Skills & Experience BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years of semiconductor industry experience.

Strong understanding of digital design fundamentals, FSMs, CDC, reset architecture, low-power design, and SoC integration.

Expertise in Verilog, System Verilog, UVM/OVM, and class-based verification methodologies.

Strong knowledge of constrained-random, coverage-driven verification, regression automation, and verification signoff.

Hands-on experience developing test benches, drivers, monitors, scoreboards, assertions, and reusable verification IP.

Experience with System Verilog Assertions (SVA), formal verification techniques, and low-power verification methodologies such as UPF/CPF.

Knowledge of industry-standard protocols including AMBA, I²C, SPI, UART, CAN, LIN, DDR, and PCIe.

Proficiency in Python, Perl, and UNIX/Linux shell scripting for automation.

Familiarity with FPGA, emulation, or prototyping platforms such as HAPS, Palladium, or Zebu is a plus.

Understanding of PMIC architectures and power management concepts is highly desirable.

Job Description We are seeking a Senior Digital Verification Engineer to develop next-generation Power Management ICs (PMICs) for automotive and industrial applications. This role will lead digital verification from architecture review through verification signoff, ensuring functionality, quality, reliability, and compliance.