Senior Analog Mixed Signal Verification Engineer

Job Title

Required Skills & Experience M.S. in Electrical Engineering, Computer Engineering, or a related field required.

Minimum 10 years of experience in analog and mixed-signal IC verification and development, including technical leadership responsibilities.

Strong understanding of analog and mixed-signal circuit fundamentals, including PMICs, DC-DC converters, LDOs, ADCs, DACs, PLLs, voltage references, bandgaps, and sensor interfaces.

Expertise in AMS verification using Verilog-AMS, System Verilog, UVM, assertions, mixed-signal simulation, and Real Number Modeling (RNM).

Experience developing behavioral models and reusable verification environments for complex mixed-signal designs.

Strong knowledge of coverage-driven verification, constrained-random verification, regression automation, and verification signoff processes.

Proficiency with industry-standard EDA tools from Cadence, Synopsys, and Siemens EDA.

Nice to Have Skills & Experience Experience with formal verification, low-power verification, and requirements traceability methodologies is highly desirable.

This role will lead analog and mixed-signal verification for automotive and industrial PMIC products from specification through verification signoff. It will also define verification strategies, environments, regressions, and coverage objectives for complex mixed-signal IPs, subsystems, and SoCs. Collaborate with cross-functional teams to ensure product quality, reliability, functional correctness, safety, and robustness.

Review product requirements, architecture specifications, design documentation, programming models, interfaces, and implementation plans for automotive and industrial PMIC applications.

Define and execute AMS verification strategies aligned with system, performance, quality, reliability, safety, power, and functional requirements.

Lead AMS verification activities, including verification plans, methodologies, environments, regressions, documentation, schedules, coverage objectives, and milestone tracking.

Develop and validate mixed-signal simulation environments, behavioral models, checkers, assertions, scoreboards, and reusable verification components using Verilog-AMS, System Verilog, UVM, and RNM.

Drive verification execution through test planning, constrained-random verification, mixed-signal simulation, coverage analysis, regression management, debug, and signoff.

Bridge digital and mixed-signal verification flows for robust block, subsystem, and top-level verification.