AMTS Verification Engineering

Responsibilities

• Develop test plans, tests and verification infrastructure for complex Block level / IP / Sub-system.
• Create verification environment using SV and UVM methodology.
• Create reusable bus functional models, monitors, checkers and scoreboards.
• Drive functional coverage driven verification closure.
• Work with the rest of the design team on design verification, debugging and bug resolution.

• Bachelor's degree in Electronics Engineering, Electrical Engineering, or Computer Engineering.
• 0-2 years of verification experience.
• Good understanding of digital design concepts.
• Good understanding of C/C++ or any OOP based programming language.
• Exposure to Verilog/System Verilog or VHDL language.
• Exposure to HVL-based verification with expertise in SV & OVM/UVM would be an asset.
• Good analytical problem solving.
• Highly motivated to learn protocols, verification flow and methodology.
• Good verbal and written communication skills.
• Knowledge of scripting languages and Linux/Unix environment would be an asset.