Principal Analog​/Power IC Design Engineer

Role Overview

As a Principal Analog / Power IC Design Engineer, you will serve as a senior technical authority responsible for the architecture, design, verification, and productization of advanced high voltage power‑management integrated circuit (IC) products. You will lead complex IC product developments as a Chip Lead, mentor engineering teams, and influence direction across multiple product and engineering disciplines. This role blends deep circuit‑level expertise, system‑level ownership, and cross‑functional leadership to deliver high‑performance, high‑reliability power solutions.

• Architecture & System Definition:
  Working with the New Product Definition team, define chip‑level and block‑level architectures and implementations for AC‑DC and DC‑DC converters, LDOs, gate drivers, power stages, digital/mixed‑signal blocks, and high‑voltage analog circuits.

• Translate system and customer requirements into robust architectures, control schemes, protection strategies, and performance targets.

• Evaluate tradeoffs in performance (e.g., efficiency, transient response, EMI, thermal behavior, etc.), risk, reliability, schedule, and cost.

• Chip Lead Responsibilities:
  Own end‑to‑end technical leadership for the entire IC program from concept through production; coordinate and align with new product definition, marketing, and all other engineering domains; drive top‑level integration, lead cross‑functional program reviews, manage technical schedules, serve as primary technical decision‑maker and escalation point, ensure chip meets performance, reliability, and manufacturability requirements across all operating conditions; represent the product team in executive, customer, and technical forums.

• Analog & Power Circuit Design:
  Lead transistor‑level design of precision analog, mixed‑signal, power, and high‑voltage circuits in high‑v BiCMOS technologies; design key blocks including bandgaps, references, amplifiers, comparators, power stages, gate drivers, level‑shifters, current/voltage sensing, oscillators, PLLs, biasing networks, protection circuits; perform advanced simulations (AC, transient, noise, stability, Monte Carlo, aging, parasitic extraction, etc.).

• Verification, Modeling & Methodology:
  Define and drive verification strategies, behavioral modeling, and mixed‑signal simulation flows; collaborate with layout team to optimize die and block floor plans, parasitics, matching, and reliability; lead design reviews and enforce best‑practice methodologies across teams and sites.

• Silicon Validation & Productization:
  Work with test engineering to define ATE test plans, DFT strategies, and production screening; lead bench/lab evaluation, silicon debug, characterization, and correlation to simulation and ATE; support reliability testing and qualification, failure analysis, and yield improvement activities.

• Cross‑Functional Technical Leadership:
  Partner with new product definition, systems, applications, product, test, device/process technology, and marketing teams to ensure product success; provide technical guidance and mentorship to junior and senior engineers and support staff; represent the design team in program reviews, customer discussions, and cross‑site/cross‑function collaborations.

• Strategic & Organizational Impact:
  Influence technology roadmaps, design methodologies, and long‑term capability development; drive continuous improvement in design flows, modeling accuracy, verification coverage, and silicon robustness; contribute to hiring, training, and developing engineering talent across the organization.

• MS or PhD in Electrical Engineering or related field.
• 12–15 years of experience in analog and power IC design with multiple successful tapeouts and product releases.
• Proven leadership in driving complex switching regulator IC products from concept to high‑volume production.
• Deep expertise in analog and power‑management design and high‑voltage CMOS/ BiCMOS/ BCD process technology.
• Familiarity with multiple switching regulator topologies and control architectures; demonstrated deep expertise in at least one topology and control scheme.
• Strong analytical, problem‑solving, and communication skills.
• Experience collaborating with cross‑functional teams across multiple sites.
• Working knowledge of Cadence simulation and layout tools.