Sr Principal Application Engineer

Job Summary

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is seeking an experienced Application Engineer to drive customer success in AI-driven digital implementation and signoff workflows. This role focuses on enabling next-generation design methodologies powered by AI, applied to backend physical design using the Innovus platform and timing signoff flows.

The ideal candidate will combine experience in AI-enabled workflows and data-driven problem solving with strong technical fundamentals in place-and-route (PnR) and static timing analysis (STA), helping customers transition to more automated and intelligent design methodologies.

• Lead adoption of AI-driven design and debug workflows (e.g., Innovus AI Assistant, agentic workflows)
• Apply AI/ML techniques to improve:
  • Design debug efficiency
  • Flow automation
  • Design convergence and optimization
• Contribute to internal and customer-facing initiatives involving:
  • LLM-based debug assistance
  • Knowledge-driven design automation
  • Multi-agent workflows for implementation and signoff
• Help define and evolve next-generation AE workflows leveraging AI capabilities

Act as a trusted technical advisor to key customers. Deliver workshops, training, and best-practice guidance, including AI-enabled workflows. Drive issue resolution across AE, PE, and R&D teams. Build long-term strategic relationships with customer design teams.

• Drive end-to-end physical design closure including floor planning, placement, CTS, routing, and optimization, congestion, power, and performance tuning
• Debug complex design issues and provide scalable solutions across blocks and full-chip designs
• Optimize PPA (Performance, Power, Area) and turnaround time (TAT) using both traditional and AI-assisted approaches

• Enable and support timing closure and signoff flows using industry-standard methodologies
• Debug timing issues including setup/hold violations, derates, variation modeling, and multi-corner/multi-mode analysis

• BS/MS in Electrical Engineering, Computer Engineering, or related field
• Demonstrated experience in: AI/ML, data-driven workflows, or automation applied to engineering problems, or digital backend design (physical design / PnR), or EDA application engineering or CAD support
• Strong technical foundation in one or more of: place-and-route (PnR) flows, static timing analysis (STA) and timing closure methodologies
• Experience working with Innovus or comparable implementation tools
• Strong debugging, problem-solving, and communication skills in complex SoC designs

• Experience with AI/ML applications in EDA, including one or more of: AI-assisted design/debug (e.g., Innovus AI Assistant, JedAI), workflow automation or data-driven optimization, experience with advanced nodes (≤7nm) and large-scale SoC or full-chip implementation
• Strong knowledge of timing signoff methodologies, including MMMC (Multi-Mode Multi-Corner), variation modeling (SOCV, AOCV), extraction and signoff correlation flows
• Hands-on experience with Cadence EDA tools (one or more strongly preferred):
  Innovus (PnR / Implementation), Tempus (STA / Signoff), Quantus (Extraction), Pegasus (Physical Verification), Genus (Synthesis)
• Prior experience in application engineering, CAD, or customer-facing roles

Help drive the transition of semiconductor design workflows toward AI-first methodologies. Influence strategic customer engagements and drive adoption of Cadence-enabled EDA solutions. Collaborate across global teams to define next-generation implementation and signoff methodologies. Travel may be required based on business needs.

Cadence is committed to equal employment opportunity throughout all levels of the organization and participates in the E-Verify program where required by law.