Verification Engineer: Automated HDL Validation
Listed on 2026-10-18
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Engineering
Test Engineer, Validation Engineer
IMC is seeking a Verification Engineer to join its R&D team in Chicago. You will verify complex hardware designs using UVM, collaborate with RTL and SW teams, and automate verification flows for rapid development.
The role requires experience with System Verilog/Verilog, C++, scripting, and Linux, plus familiarity with 3rd party EDA tools. The position offers a competitive base salary, discretionary bonus eligibility, and benefits including paid leave and insurance.
The Verification Engineer:
Automated HDL Validation position in the Engineering field is open for applications.
As a Verification Engineer:
Automated HDL Validation, you will play an important part at IMC in Chicago, IL, United States.
We invite applications for the Verification Engineer:
Automated HDL Validation position located in Chicago, IL, United States.
The following position is for a Verification Engineer:
Automated HDL Validation with IMC.
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