Package Design Engineer

AtSPDTechnology, webring together ateam oflike-minded people who are driven bythe desire tobring value through their work, united intheir commitment tohigh performance and delivering custom, cutting-edge tech solutions that drive clients’ growth. Weempower our people with aculture of excellence and enable them with the opportunity touphold their accountability to contribute oneach level. Wevalue humanity and collaboration, encourage professional and personal growth, and foster asupportive and flexible work environment where everyone’s contribution is welcomed.

And now weare looking for aPackage Design Engineertojoinus aspart ofour team.

Be part of a team pushing the boundaries of semiconductor innovation by developing custom silicon solutions that power next-generation consumer and infrastructure products. You will contribute to technologies used at massive global scale, helping shape future hardware platforms with a strong focus on performance, efficiency, reliability, and system-level integration.

As a Chip Package Designer within the Silicon Integration team, you will develop package substrate designs for advanced 2.5D/3.5D packaging technologies used in high-performance ML and AI chips.

You will collaborate closely with Signal Integrity/Power Integrity (SI/PI), Thermal/Mechanical, Assembly, and PCB engineering teams to develop complex, high-performance substrate designs. The primary objective will be to optimize package substrate architecture for electrical performance, reliability, manufacturability, and assembly.

You will manage all major phases of the package design process, including routing feasibility studies, test vehicle development, product-level designs, design reviews, artwork export, DFM activities, and preparation of final manufacturing documentation.

You will also contribute to the evaluation and adoption of advanced chip packaging technologies within the broader silicon product development pipeline. Your work will directly support successful deployment of advanced computing systems in large-scale data center environments, helping optimize PPA (Power, Performance, Area) while improving overall system performance, power efficiency, and TCO (Total Cost of Ownership).

The broader AI and Infrastructure organization is focused on building next-generation computing platforms and infrastructure at exceptional scale, efficiency, reliability, and speed. These technologies support internal engineering teams, enterprise customers, and large-scale consumer-facing services worldwide.

The organization works across both hardware and software, including custom AI accelerators, advanced silicon platforms, AI infrastructure, large-scale networking, data center technologies, distributed computing systems, and systems research.

Fully remote role. Flexible schedule with participation in team ceremonies and cross-functional collaboration.

As a qualified expert, You will:

• Develop physical package substrate design of large form-factor package for ML high-performance computers (HPCs).
• Develop and implement the methodology and CAD flow for efficient substrate design and enhanced productivity.
• Manage and drive co-design initiatives across chip, package, and system levels, including securing production sign-off for package designs.
• Collaborate closely with signal integrity/power integrity (SI/PI), thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
• Define and document the requirements for the package substrate design and bill of materials (BOM).

We’re looking for you if you have

• Bachelor’s degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science,…