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Director – PDK Architecture

Job in Clackamas, Clackamas County, Oregon, 97015, USA
Listing for: Intel Corporation
Full Time position
Listed on 2026-07-25
Job specializations:
  • IT/Tech
    Systems Engineer, IT Project Manager
Job Description & How to Apply Below

Technical Leader For PDK Architecture Team

We are seeking a highly experienced technical leader to lead the PDK Architecture team responsible for driving the technical execution of Intel's Process Design Kit (PDK) across leading-edge technology nodes. The position leads a team that serves as the technical leaders for overall PDK execution and the primary bridge between Technology Development, PDK Development, and EDA partners to ensure technology requirements are translated into scalable, high-quality, and customer-ready PDK solutions.

The role combines deep technical expertise, cross-functional leadership, customer-focus, and program execution to enable predictable and high-quality PDK deliveries for internal and external customers.

Key Responsibilities
  • Lead the definition and specification of PDK scope and content
  • Act as primary interface to Technology Definition to align and lock down inputs for PDK - ensuring Technology requirements, modeling inputs, design rules, PDK scope are defined and closed prior to execution.
  • Drive technology closure and readiness assessments across Logic, SRAM, AMS, APR, Reliability, and Packaging domains.
  • Drive technical architecture and implementation decisions for the PDK.
  • Define standards and repeatable processes to streamline and accelerate PDK development
  • Develop technology capability roadmaps and ensure PDK commitments align with technology performance objectives and customer requirements.
  • Lead executive-level reviews to identify and resolve technology readiness gaps before they impact PDK schedules.
  • Partner with Technology Development organizations to evaluate new process features, design enablement requirements, and ecosystem impact before PDK execution begins.
  • Define and execute the architecture roadmap for 3

    DIC and advanced packaging PDK solutions.
  • Drive development and release of 3DK collateral supporting heterogeneous integration technologies.
  • Ensure PDK architectures support future chiplet, system-in-package, and heterogeneous integration offerings
  • Own PDK specification methodology, quality standards, and governance processes.
  • Establish machine-readable and AI-enabled specification frameworks that improve automation and traceability.
  • Ensure specifications accurately translate technology requirements into executable PDK deliverables.
  • Drive specification signoff processes and cross-functional alignment with Technology Development and Design Enablement teams.
  • Drive quality, completeness, and traceability of PDK requirements.
  • Lead specification sign-off processes across Technology Development, PDK Development, and Design Enablement organizations.
  • Lead globally distributed teams and influence organizations across PDK Development, QA, Infrastructure and Technology Development
  • Partner with Program management for PDK execution.
Qualifications

Minimum Qualifications

  • MS or PhD in Electrical Engineering, Computer Engineering, Physics, Materials Science, or related discipline.
  • 10+ years in semiconductor technology development, design enablement, EDA, PDK development, CAD, DTCO, or related fields.
  • Strong communication and executive presentation skills.

Preferred Qualifications

  • Experience with foundry PDK development and release processes.
  • Understanding of design rules, extraction, modeling, physical verification, custom design flows, APR flows, and validation methodologies.
  • Experience working with EDA partners such as Synopsys, Cadence, and Siemens.
  • Knowledge of specification systems, automation frameworks, AI-assisted workflows, and software development methodologies.
  • Proven experience driving organizational transformation, standardization, and quality improvements.
Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Santa Clara

Additional Locations:

US, Arizona, Phoenix, US, Oregon, Hillsboro, US, Texas, Austin

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $- USDThe range displayed on this job…

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