CPU Power Engineer

Rivos Power team is seeking highly motivated candidates to develop and strategically drive state-of-the-art CPU power design, modeling, and optimization. The ideal candidate should have in-depth experience and skills for full-spectrum silicon power reduction based on solid power analysis, benchmarking, and design optimization on all levels including arch, uArch, implementation and binning on CPU blocks, and standard power-performance benchmarking.

You will have the opportunity to work with architecture, uArch design, design verification, circuit and physical design, and silicon validation teams to drive towards a power-efficient design. The role will be at the center of a state-of-the-art power design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly.

• Drive the task of power design for CPU blocks across different teams including Arch, uArch, implementation, performance, DV and testing teams.
• Model and own uses-cases and workloads for custom silicon working closely with the CPU architecture, Performance and IP teams to determine the overall power requirements.
• Analyze and deploy trade-offs between CPU power and performance and drive detailed cost/benefit analysis and making recommendations for power reduction.
• Create test vectors with the performance, design verification and RTL teams to model the appropriate workloads, and the correct functionality scenarios for simulation.
• Own power simulations, analysis, tuning, correlation, and rollup to the architecture, logic design, and physical design teams.
• Collaborate with the CAD and Physical design implementation teams on power estimation, simulation flow, and regression analysis.
• Interact with software and system-level teams to influence SoC and product level power.

• 8 to 15 years experience in CPU power design including design analysis, benchmarking, modeling and simulation.
• Experience and working knowledge of CPU architectures and workload modeling for power. RISC-V architecture familiarity and experience is a plus.
• Familiarity with Verilog and System Verilog RTL coding.
• Experience in silicon design flow and evaluating PPA tradeoffs at architecture, logic and circuit design levels.
• Knowledge of device physics, advanced process technology and circuit design fundamentals is a plus.
• Experience in state-of-the-art EDA tools for gate and transistor level power modeling and simulations.
• Python, TCL and other scripting languages.
• Aptitude to problem-solve on the fly, innovate, drive decisions and bring the team along to deliver under aggressive schedules.

• EE/ EECS degree with 8-15 years of industry experience.

$200,000 - $230,000 a year

• Mid-Senior level

• Full-time

• Engineering and Information Technology

• Computer Hardware Manufacturing