PCIe Gen​/GenFunctional Post-Silicon Validation Engineer

Senior PCIe Gen6/Gen7 Functional Post-Silicon Validation Engineer

Duration:
Contract

Experience: 7+ Years

We are seeking a highly motivated Senior PCIe Gen6/Gen7 Functional Post-Silicon Validation Engineer to lead validation of next-generation PCIe Switch and Retimer silicon.

This role focuses on functional and protocol-level validation of Gen6/Gen7 devices, ensuring robust specification compliance by validating LTSSM behavior, link training, equalization flows, configuration space, data path integrity, and advanced error handling.

You will collaborate closely with Architecture, Design, RTL, and Firmware teams to deliver high-quality silicon solutions.

• Lead post-silicon bring-up and functional validation of PCIe Gen6/Gen7 Switch and Retimer devices
• Develop and execute detailed functional validation test plans
• Cover LTSSM transitions and link initialization sequences
• Verify configuration space and capability structures
• Verify flow control and credit management
• Validate posted, non-posted, and completion TLP traffic
• Verify ASPM and L1 substates

• Validate multi-port and multi-host switch configurations
• Validate FLIT mode operation
• PAM4 functional behavior
• Enhanced error containment
• Debug LTSSM, link training, enumeration issues
• Develop Python automation frameworks and regression suites
• Work with RTL and Firmware teams to root cause issues
• Document coverage and validation results

• Hands-on debugging of LTSSM failures, link training issues, transaction layer bugs
• Experience validating PCIe Switch or Retimer silicon
• Deep knowledge of TLP/DLLP, credit logic, replay buffers
• Professional experience with Python automation

• CXL protocol knowledge
• Compliance workshop / interoperability event experience