Design Verification Engineer

Design Verification Engineer

Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom’s ASIC developments.

Position

Description:

The engineer will be responsible for defining verification plans and environment architecture, developing test cases and test bench components, coverage analysis and closure, and debugging. This position may involve working with emulation and FPGA prototyping platforms and leading efforts in evaluating and driving the adoption of advanced verification methodologies/flows. The engineer will be expected to develop functional models to facilitate block, system, and ASIC level verification.

The candidate must work closely with design teams and EDA vendors to accomplish the modeling and verification tasks.

The candidate must have experience using System Verilog and UVM, designing verification components including UVM agents, checkers, and behavioral models. Experience with implementing and achieving coverage goals by developing random and directed test cases and System Verilog Assertions. The engineer will be responsible for analyzing and debugging simulation failures at the RTL and gate level. The engineer must be knowledgeable of RTL, gate-level netlists, and SDF and capable of analyzing such formats in the verification context.

• 6+ years of experience with verification concepts and architectures for complex digital and MXS circuits
• Experience verifying designs at the block and system levels
• Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
• Experience debugging RTL and gate-level netlists, analyzing schematic diagrams of analog and MXS circuits
• Experience using System Verilog and advanced verification concepts and methodologies (UVM, SVA)
• Experience with Synopsys, Cadence, and Mentor simulation tools
• Demonstrated ability to plan and deploy complex, reusable, and scalable verification environments
• Experience with Perl/Python and Tcl or other scripting languages
• Experience with version control systems (Design Sync, git)
• Superior writing, grammar, and verbal communication skills
• Excellent problem‑solver; develops and employs automated processes where applicable
• Worked independently and in a global team and dynamic environment in a highly visible role
• Possesses ability to learn and adapt to new tools and methodologies on the fly
• Must have legal authorization to work in the US

• Experience with hardware design and debug
• Experience with emulation (Palladium, Veloce, Zebu) and FPGA (Xilinx) platforms
• Formal verification concepts or experience is a plus
• Experience verifying iJTAG network using ICL and PDL in the Tessent tool
• Experience with co‑simulation is a plus

• BS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience.

The annual base salary range for this position is $108,000 - $172,800. As a valued member of our team, you will be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new‑hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.