ASIC Design Engineer - Low-Power CNN Accelerator

Tensordyne seeks an experienced ASIC designer to drive microarchitecture and RTL implementation for a high-performance CNN accelerator used in autonomous driving. The role focuses on end-to-end RTL, verification, and integration with CPU IP within a SoC context.

You will collaborate with design teams to meet timing and power targets, support frontend/back-end flows, and assist with post-silicon validation and software bring-up in a dynamic startup environment.

We have an opening for a ASIC Design Engineer
- Low-Power CNN Accelerator in United States within Engineering.

This role, ASIC Design Engineer
- Low-Power CNN Accelerator at Tensordyne, could be your next move.

Are you ready to take on the ASIC Design Engineer
- Low-Power CNN Accelerator role at Tensordyne?

We would love to welcome a new ASIC Design Engineer
- Low-Power CNN Accelerator to our team in United States.