FPGA Verification Engineer

Overview

• Title:
  
  FPGA Verification Engineer
• Headcount: 8
• Location:
  
  Costa Mesa, CA onsite
• Travel: 0% onsite
• Contract:
  
  Full-time;
  Start: ASAP
• Interview Process:
  Phone screen, technical interview, final interview;
  Feedback SLA: 48 hours
• Why Hiring:
  Need to enhance FPGA verification capabilities;
  Support rapid avionics development
• End Product:
  Verification environments for AMD (Xilinx) FPGA/SoC designs in flight-critical avionics
• Tech/Domain Environment:
  System Verilog, UVM, SVA;
  Linux; DO-254, avionics standards;
  Questa, VCS, Xcelium, Vivado

• Architect UVM verification environments for AMD FPGA/SoC designs.
• Develop verification plans with traceability to requirements.
• Author System Verilog Assertions for compliance checks.
• Build functional coverage models and drive code coverage analysis.
• Develop constrained-random test sequences for corner-case bugs.
• Establish regression suites, tracking coverage metrics.
• Debug failures using waveform tools and simulation logs.
• Collaborate on RTL reviews and bug resolution.
• Support hardware validation and board bring-up.
• Author verification closure reports and coverage summaries.

• 2+ years FPGA/ASIC verification experience in production.
• Proficient in System Verilog, UVM methodology, and SVA in production.
• Experience with industry simulators (Questa, VCS, Xcelium, or Vivado) in production.
• Git-based workflows including code review in production.
• Linux development environments in production.
• Eligible for U.S. Secret security clearance.

• 5+ years FPGA/ASIC verification experience.
• Master’s degree in Electrical or Computer Engineering.
• Experience with DO-254 and avionics verification standards.
• Familiarity with SVUnit or equivalent unit-testing frameworks.
• Experience with digital interfaces:
  Ethernet, PCIe, JESD
  204C, MIL-STD-1553, SPI.

• No experience in FPGA/ASIC verification.
• Only academic/POC experience with UVM.
• No experience with industry simulators in production.

• Coverage metrics to closure, p99 < 95% for verification success.

• Eligible to obtain U.S. Secret security clearance.