DRAM PHY Designer

Job Title

PHY and IO Design for Memory-Centric Compute Systems

Qualcomm Semiconductor Limited

Engineering Group, Engineering Group > ASICS Engineering

Qualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform high performance AI and connected computing potential into world-changing technologies and products.

This is the Invention Age - and this is where you come in.

The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of PHY and IO design for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will develop high-speed PHY that connects compute and memory bus in memories to the various channels in the package, interposers, and board that connects memory to compute and memory pools.

The candidate should have good knowledge of high-speed and low-energy memory PHY design. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential.

• Architect, design, and implement high-speed PHY circuits
• Create layouts that optimize circuit placement, signal routing, and power delivery
• Develop robust power delivery to the PHY design
• Simulate signal integrity and SNR performance together with the package and board s-parameter model
• Simulate pre-layout and post-layout mixed-mode circuits under PVT corners
• Incorporate power management features to reduce energy consumption
• Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness
• Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads
• Floorplan PHY circuits under manufacturing constraints, testability, repairability, and high performance

• Knowledge of timing circuits such as DLL, PLL
• Knowledge of analog building blocks
• Knowledge of SERDES, phase and duty cycle adjustment circuits
• Knowledge of LPDDR, HBM, and IO interfaces
• Knowledge of eye diagram and noise sources
• Master's or Ph.D. in Electrical Engineering and a related field

• Familiar with package design
• Experience in scripting language (Perl/Python)
• Familiar with the DRAM datasheets and IO interfaces

• Self-Starter with good communication skills and team-working spirit
• Strong problem-solving and analytical skills
• Ability to work independently and as part of a team

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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