DRAM Circuit Designer

Job Title

Qualcomm Memory System/Technology Team in Process & Package Solutions Group

Qualcomm Semiconductor Limited

Engineering Group, Engineering Group > ASICS Engineering

Qualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform high performance AI and connected computing potential into world-changing technologies and products.

This is the Invention Age - and this is where you come in.

The Qualcomm Memory System/Technology Team in Process & Package Solutions Group has an opening in the areas of custom DRAM design and architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will design circuits for the custom DRAM to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will work on solutions addressing manufacturability and repairability of the circuits.

The candidate is expected to know the DRAM circuit design in the domains of DRAM bank circuits such as decoder, sense amplifier, datapath, and voltage generation circuits. The candidate should have familiarity with the bus and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, and emulation team.

Providing timely feedback and updating architecture and design trade-offs to the team is essential.

• Design and optimize memory core circuits for higher sense margin, improved array timing, area
• Develop and optimize DRAM circuits and timing control for performant, area, and energy efficient cell array
• Develop bank array placement strategies across various bank array, TSV, and power distribution choices
• Develop novel fabrics for best/robust distribution of high-bandwidth busses across the DRAM array, compute, and IO
• Create layouts that optimize circuit placement, signal routing, and power delivery
• Develop robust power delivery to the array design
• Use state-of-the-art design and simulation tools to simulate the circuit behavior and manufacturability readiness
• Develop behavioral, timing, and power models of the circuits to guide the architecture choices across AI, compute, and mobile workloads
• Floorplan DRAM circuits under manufacturing constraints, testability, repairability, and high performance

• Experience in mixed-signal design, layout, and simulation
• Knowledge of high-speed design principles and reliability
• Experience in memory array and datapath design (SRAM/DRAM/Flash/ROM/OPT, etc)
• Ability to develop Verilog/Verilog-A/Verilog-AMS models of critical dataflow is strong plus
• Proficiency in use of EDA tools, Matlab, and Phyton
• Good knowledge of memory architecture, buses, and 2.5D/3D integration
• Master's or Ph.D. in Electrical Engineering and a related field

• Experience in DRAM architecture performance assessment
• Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python)
• Familiar with the DRAM datasheets and IO interfaces

• Self-Starter with good communication skills and team-working spirit
• Strong problem-solving and analytical skills
• Ability to work independently and as part of a team

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Applicants:
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