VLSI Design Engineer: RTL, ASIC Innovation Speed Protocols
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-02-16
Listing for:
Retym Israel Ltd
Full Time
position Listed on 2026-02-16
Job specializations:
-
Engineering
Systems Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
A leading technology company seeks a talented VLSI Design Engineer to design cutting-edge communication systems. This role requires over 5 years of experience with strong Verilog/System Verilog skills and collaboration with teams across the design process. Ideal candidates will have a BS/MS in Electrical or Computer Engineering and should be familiar with advanced design practices and EDA tools. Join us to innovate in the VLSI domain and contribute to industry-leading projects in California.
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