Design Verification Engineer

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs.

This is a critical job within Apple's Hardware Technology organization, and we'd love to have you join us.

As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design u0026 micro-architecture teams. A key component to the job is understanding the functional u0026 performance goals of the design and you use this knowledge to test optimally.

You develop test plans, tests u0026 coverage plans as well as define our next generation verification methodology u0026 test benches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:

- Neural Engine hardware - DRAM subsystem, memory controller logic - Encode and Decode systems for Pro Res and other codec formats such as VP9, AV1 - Hardware security, including cryptographic algorithm implementations - High-Speed IO standards such as PCI Express, Display Port, MIPI - Power management and fabric infrastructure - Memory cache management - Display Subsystem for variety of panels and products.

These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It's up to you!

Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology u0026 philosophy Knowledge of System Verilog, digital simulation and debug Knowledge of computer architecture and digital design fundamentals SW programming skills with knowledge of data structures and algorithms

Experience with Python, Perl, or similar scripting language Ability to work independently to deliver the project goals Knowledge of verification methodologies like UVM

Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges.

Minimum of BS + 3 years relevant industry experience.