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MLB Reliability Hardware Position

Job in Cupertino, Santa Clara County, California, 95014, USA
Listing for: OSI Engineering
Full Time position
Listed on 2026-05-16
Job specializations:
  • Engineering
    Electrical Engineering, Electronics Engineer, Mechanical Engineer, Quality Engineering
Salary/Wage Range or Industry Benchmark: 60000 - 80000 USD Yearly USD 60000.00 80000.00 YEAR
Job Description & How to Apply Below

Our client, a leading innovator in consumer electronics and silicon technologies, is seeking a Hardware Reliability Engineer to join their Hardware Reliability Engineering team.

In this role, you will be responsible for executing reliability testing on Main Logic Boards, identifying hardware module integration issues through FMEA, conducting system reliability testing and failure analysis, and quantifying the reliability of complex product designs. This is a highly technical, hands‑on engineering role ideal for someone who thrives in deep analysis, problem‑solving, and cross‑functional collaboration.

Responsibilities
  • Develop and execute detailed reliability test plans.
  • Compile and analyze test and failure data.
  • Perform statistical data analysis to provide risk assessments for product designs.
  • Research failure modes for new technologies and conduct extensive FMEA (Failure Modes & Effects Analysis).
  • Execute mechanical stress tests including shock, drop, vibration, and environmental testing.
  • Perform system‑level reliability testing and failure analysis.
  • Quantify and model reliability performance of silicon‑based designs.
  • Provide design recommendations to cross‑functional teams to improve product reliability.
  • Prioritize and complete tasks to meet project deadlines.
  • Communicate findings clearly to cross‑functional engineering teams and senior leadership.
Requirements
  • 3+ years of hands‑on experience performing reliability testing.
  • Experience with mechanical stress tests including shock, drop, vibration, and environmental testing.
  • Strong understanding of failure analysis techniques such as Optical Microscopy, X‑Ray, SEM/EDS, FTIR, and XPS.
  • Knowledge of JEDEC and IPC standards for semiconductor package qualification.
  • Experience with silicon product‑level reliability qualification, associated failure modes, and lifetime behavior modeling.
  • Strong analytical and problem‑solving skills.
  • Excellent written and verbal communication skills.
  • Ability to provide concise executive‑level summaries and lead in‑depth technical discussions.
  • Strong attention to detail, particularly during early architecture and design phases.
  • Ability to manage multiple projects simultaneously.
  • Collaborative, proactive, and enthusiastic team contributor.
Education
  • Bachelor’s degree in Mechanical Engineering, Electrical Engineering, Materials Science, or a related field.
  • Master’s or PhD preferred.
  • Experience with semiconductor packaging or consumer electronics is a plus.

Duration: 4 months with the possibility of extension

Location: Hybrid 3+ days a week in Cupertino, CA

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