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Physical Design Engineer Speed ICs & Low Power

Job in Cupertino, Santa Clara County, California, 95014, USA
Listing for: Neethaconsulting
Full Time position
Listed on 2026-06-04
Job specializations:
  • Engineering
    Electrical Engineering, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 145000 USD Yearly USD 125000.00 145000.00 YEAR
Job Description & How to Apply Below
Position: Physical Design Engineer - High-Speed ICs & Low Power

Job Title:

Physical Design Engineer

Salary Range:

$125,000 – $145,000 per year (commensurate with experience)

Location:

USA

Job Duration:

Full-time, 40 hours/week, permanent position

Job Duties:
  • Conceptualize, design, and productize advanced RTL to GDS implementations through ASIC design flow.
  • Lead the physical design closure process including floor planning, placement, clock tree synthesis, routing, and optimization.
  • Develop efficient IC block layouts optimized for area, timing, and power at advanced technology nodes (e.g., TSMC N5/N4P/N3).
  • Drive implementation of high-performance, low-power, manufacturable designs.
  • Perform synthesis, pre‑layout STA, SDC constraints development, bump placement, power planning, MV design techniques, and UPF.
  • Apply timing closure techniques: clock skew balancing, delay optimization, OCV handling, and ECO management.
  • Conduct power and area optimization using Multi‑VT, clock gating, and power‑aware synthesis.
  • Manage post‑layout STA, functional/timing ECOs, and high‑frequency IP designs closure.
  • Ensure physical verification (DRC, LVS, PERC, ERC, Antenna, EMIR, Power signoff) compliance with foundry sign‑off standards.
  • Collaborate with cross‑functional teams to resolve design and manufacturing issues.
  • Drive scripting and automation (Python, Perl, TCL) to enhance design efficiency.
  • Use EDA tools (Innovus, ICCII, Fusion Compiler, Tempus, Prime Time) for implementation and signoff readiness.
Other Responsibilities:
  • Mentor junior engineers and review design outputs.
  • Document physical design flows, constraints, and reports.
  • Implement and improve methodologies, workflows, and tools for better process quality and efficiency.
Job Requirements:

Master’s or foreign equivalent in Electrical Engineering, Computer Engineering, or related field. Must be able to travel/relocate to various client sites across the U.S.

Location of Work:

Neetha Consulting LLC 10080 North Wolfe Road, Suite SW3‑200 Cupertino, CA 95014

How to Apply:

Send your resume to: or apply by filling out the form on our website.

Ready to Accelerate Your Chip Design Journey?

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