Senior Physical Design Engineer: Timing, Floorplanning & P&R

A leading technology company is seeking a Physical Design Engineer to contribute to the design of high performance PHY from RTL to GDSII. Responsibilities include generating timing constraints, building chip floor-plans, and validating designs adhering to power and timing requirements. The ideal candidate has a

B.Sc. in Electrical Engineering and relevant experience in SoC designs. The base pay for this role ranges from $126,800 to $220,900 based on experience and qualifications. Comprehensive benefits including stock purchase programs and education reimbursement are offered.
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