Sr. Physical Design Verification Engineer, Annapurna Labs

Sr. Physical Design Verification Engineer, Annapurna Labs

Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

• Drive full chip floorplan, integration, and physical verification sign‑off and closure.
• Define, execute and optimize next‑generation physical verification and integration methodologies using industry‑standard EDA tools (Calibre, IC Validator).
• Perform DRC, LVS, PERC verification, and fill insertion.
• Debug and resolve physical verification issues in collaboration with layout and design teams.
• Interface with foundries for MT form, rule deck updates and violation waivers.
• Develop and maintain verification runsets and methodologies.
• Support technology file development and qualification.
• Fine‑tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Mentor junior engineers on physical verification methodologies and closure.

• Experience in Python, Perl, or another scripting language.
• BS + 10 yrs or MS + 7 yrs in EE/CS, or related field.
• 5+ years in physical verification for advanced technology nodes.
• Expert knowledge of industry‑standard physical verification tools (Calibre, IC Validator, PVS).
• Strong understanding of semiconductor manufacturing processes and design rules.
• Proven track record of successful tape‑outs.
• Strong communication and collaboration abilities.
• Design flow knowledge: understanding of backend physical design flows (FC/Innovus).

• Experience with integration and verification in advanced nodes (5 nm or below).
• Knowledge of custom and digital design flows.
• Expertise with DFM methodologies.
• Expertise in reliability verification (ESD, EM, IR drop).
• Background in layout design or custom IC development.

• Cupertino, CA
• Austin, TX

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