ASIC STA Engineer: Timing Closure & IP Delivery
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-07-18
Listing for:
Apple Inc.
Full Time
position Listed on 2026-07-18
Job specializations:
-
Engineering
Electronics Engineer, Hardware Engineer, Systems Engineer
Job Description & How to Apply Below
Apple Inc. in Cupertino seeks an ASIC STA Engineer to lead timing closure across complex SoCs. You will own timing closure for full chips and blocks, guiding timing verification and constraint generation across projects.
Work with multi-functional teams to resolve timing issues in deep sub-micron technologies. Strong digital design fundamentals and scripting in TCL/Perl are valuable, with Primetime familiarity a plus.
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