Senior ASIC Timing & STA Engineer
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-07-18
Listing for:
Apple Inc.
Full Time
position Listed on 2026-07-18
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer, Quality Engineering, Manufacturing Engineer
Job Description & How to Apply Below
Apple Inc. is seeking an experienced ASIC STA Engineer in Cupertino to drive timing closure across all SoC stages. You will own timing constraints, sign-off activities, and collaborate with RTL, CAD, and Physical teams to achieve timing goals.
You will apply expertise in Primetime and scripting to streamline flows, improve closure reliability, and contribute to the design of next-generation Apple silicon.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×