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Senior ASIC Physical Design Engineer – Tapeouts & PV
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-07-18
Listing for:
Amazon
Full Time
position Listed on 2026-07-18
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
Annapurna Labs, a part of Amazon, is seeking a SOC Top Level Physical Design Engineer to help design and optimize hardware for AWS data centers. You’ll own the full chip floorplan, placement, integration, and tapeout, collaborating with FE teams to align RTL with physical implementation.
The role requires strong experience in physical verification, backend design flows (FC/Innovus), and industry tools like Calibre and IC Validator.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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