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SoC DV Engineer - Verilog, UVM & Testbench Expert
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-07-18
Listing for:
Apple Inc.
Full Time
position Listed on 2026-07-18
Job specializations:
-
Engineering
Test Engineer
Job Description & How to Apply Below
Apple Inc. in Cupertino, CA is seeking a Design Verification Engineer to verify functionality and performance of Apple's premier SOCs.
You will review design specs, test benches, and work with design, architecture, and software teams to drive verification coverage. The role requires a BS + 3+ years experience, strong knowledge of Verilog/System Verilog, digital design fundamentals, and scripting (Python/Perl).
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