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Senior ASIC Physical Design Engineer – Tapeout & Optimization
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-07-27
Listing for:
Amazon Web Services (AWS)
Full Time
position Listed on 2026-07-27
Job specializations:
-
Engineering
Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
Annapurna Labs (U.S.) Inc. is seeking an ASIC Physical Design Engineer to drive full chip floor planning, placement and tapeout within AWS data centers. You will collaborate with FE and sign off PV using industry tools, while ensuring high design quality and robust trade-offs.
The role requires strong scripting, 5+ years in physical verification, and experience with FC/Innovus, Calibre, IC Validator and PVS. Excellent communication and mentoring abilities are essential.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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