Senior ASIC Physical Design & Timing Engineer
Job in
Cupertino, Santa Clara County, California, 95014, USA
Listed on 2026-07-30
Listing for:
Amazon
Full Time
position Listed on 2026-07-30
Job specializations:
-
Engineering
Electronics Engineer, Automation & Mechatronics Engineer, Hardware Engineer
Job Description & How to Apply Below
Amazon is seeking an experienced engineer for the Cloud-Scale Machine Learning Acceleration team, focusing on ASIC timing. You will design and optimize timing flows for block and full‑chip RTL-to-GDSII, write and validate constraints, and automate STA processes.
You will mentor teammates and collaborate across RTL, Arch, and physical design teams to improve performance and cost. The role requires strong scripting experience and a deep understanding of ASIC physical design and sign-off
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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